The present invention relates generally to a method for forming a capacitor and, more specifically, to a method for forming a deep trench capacitor.
Advancement in chip technology means logic switching and data transfer rates continually increase. This makes power supply decoupling more critical for system performance, yet has the effect of making the problem of power supply decoupling more difficult. Current on-chip decoupling capacitors invariably consume silicon real estate, which can temper area reductions from CMOS scaling. Even back-end-of-the-line (BEOL) capacitors often have requirements on what is placed underneath them. BEOL capacitors can consume wiring channels above or below the capacitor. Conventional deep trench capacitors offer good capacitance density, but consume silicon area. BEOL capacitors typically have low capacitance density compared to front-end-of-the-line (FEOL) capacitors, which benefit from comparatively thinner dielectrics. Therefore, a continuing need exists for technologies which can reduce area consumed by decoupling capacitors.